The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
As merely one example, semiconductor lithography processes may use lithographic templates (e.g., photomasks or reticles) to optically transfer patterns onto a substrate. Throughout a fabrication process, such patterns may be periodically measured in order to maintain a high degree of overlay control (e.g., pattern-to-pattern alignment). With the continued scaling of IC dimensions, coupled with new patterning techniques (e.g., such as double patterning), accurate overlay control is more critical than ever. As such, there is a great deal of interest in metrology tools and techniques capable of accurately measuring these extremely scaled patterns. In at least some existing methods, a signal corresponding to a main pattern feature may be impacted by a signal from a neighboring pattern (e.g., due to tight pattern pitch). Furthermore, signal crosstalk (e.g., along different planes) may also detrimentally effect pattern measurement.
Thus, existing techniques have not proved entirely satisfactory in all respects.